#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
struct {
	struct jailhouse_system header;
	__u64 cpus[1];
	struct jailhouse_memory mem_regions[11];
	struct jailhouse_irqchip irqchips[4];
  struct jailhouse_pci_device pci_devices[1];
} __attribute__((packed)) config = {
.header = {
		.signature = JAILHOUSE_SYSTEM_SIGNATURE,
		.revision = JAILHOUSE_CONFIG_REVISION,
		.flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
	.hypervisor_memory = {
		.phys_start = 0xc0200000,
		.size = 0x1000000,
	},
	
	.debug_console = {
		.address = 0xfeb50000, 
		.size = 0x100, 
			.type = JAILHOUSE_CON_TYPE_8250,
			.flags = JAILHOUSE_CON_ACCESS_MMIO |
				 JAILHOUSE_CON_REGDIST_4,
	},
 

	.platform_info = {
		.pci_mmconfig_base =   0xf1000000,  
		.pci_mmconfig_end_bus = 0, 
		.pci_is_virtual = 1, 
		.pci_domain = 1,
		.arm = {
			.gic_version = 3,
			.gicd_base = 0xfe600000,
			.gicr_base = 0xfe680000,
		//	.gicc_base = 0xfe6c0000,
			//.gich_base = 0xfe680000,
		//	.gicv_base = 0xfff20000,
			.maintenance_irq = 25,
		},
	},
		.root_cell = {
		.name = "RootCell",
		.cpu_set_size = sizeof(config.cpus),
		.num_memory_regions = ARRAY_SIZE(config.mem_regions),
		.num_irqchips = ARRAY_SIZE(config.irqchips),
   .num_pci_devices = ARRAY_SIZE(config.pci_devices),
		.vpci_irq_base = 496-32,
	},
},
.cpus = { 0xff, },
.mem_regions = {

  	/*ivshmem*/
		{
			.phys_start = 0x45000000,
			.virt_start = 0x45000000,
			.size = 0x10000,
			.flags = JAILHOUSE_MEM_READ,
		},
				{
			.phys_start = 0x45010000,
			.virt_start = 0x45010000,
			.size = 0x90000,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
		},
				{
			.phys_start = 0x450a0000,
			.virt_start = 0x450a0000,
			.size = 0x20000,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
		},
				{
			.phys_start = 0x450c0000,
			.virt_start = 0x450c0000,
			.size = 0x20000,
			.flags = JAILHOUSE_MEM_READ,
		},
				{
			.phys_start = 0x450e0000,
			.virt_start = 0x450e0000,
			.size = 0x20000,
			.flags = JAILHOUSE_MEM_READ,
		},
	{.phys_start=0x0, .virt_start=0x0, .size=0x00200000, .flags=JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO},
	{.phys_start=0x00200000, .virt_start=0x00200000, .size=0xefe00000, .flags=JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE},
   	{.phys_start=0xf0000000, .virt_start=0xf0000000, .size=0x2200000, .flags=JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO},
	{.phys_start=0xf2200000, .virt_start=0xf2200000, .size=0xcef0000, .flags=JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO},
	{.phys_start=0x100000000, .virt_start=0x100000000, .size=0x2fff00000, .flags=JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE},
	{.phys_start=0x980000000, .virt_start=0x980000000, .size=0xc1400000, .flags=JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO},

},

.irqchips = {
	{
		.address = 0xfe600000, 
		.pin_base = 32, 
		.pin_bitmap = {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}, 
	},
 /* GIC */ {
			.address = 0xfe600000,
			.pin_base = 160,
			.pin_bitmap = {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}, 
		},
   
   /* GIC */ {
			.address = 0xfe600000,
			.pin_base = 288,
			.pin_bitmap = {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}, 
		},
   
   /* GIC */ {
			.address = 0xfe600000,
			.pin_base = 416,
			.pin_bitmap = {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}, 
		},
},
.pci_devices = {
		{ 
			.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
			.domain = 1,
			.bdf = 0 << 3,
			.bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
			.shmem_regions_start = 0,
			.shmem_dev_id = 0,
			.shmem_peers = 3,
			.shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
		},
	},
};
